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Espressif Systems /ESP32-S2 /I2C0 /SCL_HIGH_PERIOD

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Interpret as SCL_HIGH_PERIOD

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SCL_HIGH_PERIOD0SCL_WAIT_HIGH_PERIOD

Description

Configures the high level width of the SCL clock

Fields

SCL_HIGH_PERIOD

This register is used to configure for how long SCL remains high in master mode, in I2C module clock cycles.
SCL_WAIT_HIGH_PERIOD

This register is used to configure for the SCL_FSM’s waiting period for SCL to go high in master mode, in I2C module clock cycles.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data